Bipolar transistors are useful for performing logic operations in applications in which speed is critical. One use of bipolar transistors is emittercoupled logic (ECL) technology, which is extremely fast, but also consumes more current than other technologies such as transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS) technologies. As manufacturing processed have improved, it has become possible to combine two or more technologies to receive the benefit of the best features of each. CMOS may be combined with TTL or ECL to provide a circuit that is very fast and which consumes a relatively small amount of power. For example, an integrated circuit memory may have a memory core comprised of CMOS memory cells, but input/output circuits comprised of TTL or ECL logic. The memory will be very fast, but consume only slightly more power than a CMOS-only design, since the high-power TTL or ECL circuitry is confined to those circuits which determine the access time of the memory and which are shared between many or all memory cells.
With the emergence of integrated circuit processing techniques capable of fabricating circuits with CMOS and TTL or CMOS and ECL transistors, reducing the high power consumption of TTL or ECL has become more important. FIG. 1 shows a known ECL circuit 20 in which employs a technique to reduce power consumption disclosed in "ECL ICs Play a Role in High-Speed Computers" by John Gallant, EDN vol. 34, no. 17, pp. 73-85, 80 (Aug. 17, 1989). Circuit 20 generally comprises in input stage 22, a biasing stage 24, and an output stage 26. Also shown in FIG. 1 is a capacitor 28 forming a load for circuit 20. Input stage 22 comprises resistors 30 and 31; NPN transistors 32, 33, and 34; and a resistor 35. Biasing stage 24 comprises an NPN transistor 40, a resistor 41, and a capacitor 42. Output stage 26 comprises NPN transistors 50 and 51.
Resistors 30 and 31 each have a first terminal connected to a power supply voltage terminal labelled "V.sub.DD ", and a second terminal. V.sub.DD is a positive power supply voltage terminal. Transistor 32 has a collector connected to the second terminal of resistor 30, a base for receiving an input signal V.sub.IN+, and an emitter. Transistor 33 has a collector connected to the second terminal of resistor 31, a base for receiving an input signal V.sub.IN-, and an emitter. Transistor 34 has a collector connected to the emitters of transistors 32 and 33, a base for receiving a reference voltage labelled "V.sub.BIAS ", and an emitter. Resistor 35 has a first terminal connected to the emitter of transistor 34, and a second terminal connected to a power supply voltage terminal labelled "V.sub.SS ". V.sub.SS is a negative power supply voltage terminal. Transistor 40 has a collector connected to a power supply voltage terminal labelled V.sub.DD, a base for receiving a voltage labelled "V.sub.CLAMP ", and an emitter. Resistor 41 has a first terminal connected to the emitter of transistor 40, and a second terminal connected to V.sub.SS. Capacitor 42 has a first terminal connected to the second terminal of resistor 30, and a second terminal connected to the emitter of transistor 40. Transistor 50 has a collector connected to V.sub.DD, a base connected to the second terminal of resistor 31, and an emitter coupled to a load and providing a signal labelled "V.sub.OUT " thereon. Shown here is a capacitive load represented by a capacitor 28 having a first terminal connected to the emitter of transistor 50, and a second terminal connected to V.sub.SS. Transistor 51 has a collector connected to the emitter of transistor 50, a base connected to the emitter of transistor 40, and an emitter connected to V.sub.SS.
In operation, circuit 20 alternately charges and discharges a primarily capacitive load, represented by load capacitor 28, in response to a difference in voltage between V.sub.IN+ and V.sub.IN-. Input stage 22 provides true and complementary voltages on the second terminal of resistor 31 and on the second terminal of resistor 30, respectively, in response to a difference in voltage between V.sub.IN+ and V.sub.IN-. V.sub.BIAS biases transistor 34 to substantially operate as a current source. When the voltage on V.sub.IN+ rises above V.sub.IN-, then transistor 32 becomes more conductive than transistor 33, the voltage on the collector of transistor 33 rises, and eventually forward biases the base-emitter junction of transistor 50. The collector-base junction is reverse biased, so transistor 50 provides a charging current into load capacitor 28 as determined by the current gain, or .beta., of transistor 50. If the base-emitter diode cutin voltage is labelled "V.sub.BE1 ", V.sub.OUT rises to approximately V.sub.DD -V.sub.BE1. Note that as the voltage on the second terminal of resistor 30 falls, the voltage on the first terminal of capacitor 42 drops as well, and the excess charge on the second terminal of capacitor 42 discharges through resistor 41 to V.sub.SS. The voltage on the second terminal of capacitor 42 eventually falls to a low voltage, but is limited by transistor 40 to be no lower than V.sub.CLAMP minus V.sub.BE40, where V.sub.BE40 is the cutin voltage of the base-emitter diode of transistor 40.
When V.sub.IN+ falls below V.sub.IN-, the voltage on the collector of transistor 33 falls, reverse biasing the base-emitter diode of transistor 50. The voltage on the collector of transistor 32 rises, and the voltage on the base of transistor 51 rises in response thereto, due to the coupling effect of capacitor 42. The base-emitter junction of transistor 51 is now forward biased, the collector-base junction is reverse biased, and therefore transistor 51 conducts current from the load to V.sub.SS in response to .beta. times the base current. However, the voltage on the second terminal of capacitor 42 falls due to the relaxation of current in resistor 41, and also some base current in transistor 51. When eventually the base-emitter junction of transistor 51 is no longer forward biased, no more discharging current can flow from load capacitor 28 to V.sub.SS.
By making pulldown transistor 51 conductive only when V.sub.OUT is still at a logic high, biasing stage 24 ensures that only small amounts of quiescent current flow in circuit 20 after capacitor 28 is discharged by transistor 51. However there is a limitation with this approach because capacitor 42 requires a certain amount of time to charge while V.sub.IN+ exceeds V.sub.IN-. For example, if V.sub.IN+ changes from a logic low to a logic high, and then again back to a logic low quickly, capacitor 28 cannot recharge enough to bias transistor 51 to discharge the load. Therefore circuit 20 is not appropriate for applications in which V.sub.IN+ and V.sub.IN- switch very quickly between states. However, it is well known in the art that such limitations may be tolerable when available manufacturing technology affords no alternatives, as for example when the available manufacturing technology does not include the ability to manufacture PNP transistors.